Wireless Communication Based Evaluation of Power Consumption for Constrained Energy System

The estimation of power consumption for various wireless systems involves complex computational algorithms for digital signal processing, as accessing and implementing these algorithms in the form of hardware is critical. There is therefore a need to design energy-intensive wireless communication systems. This paper presents a novel method based on the evaluation of practical systems implemented by the Application Specific Integrated Circuit and Field Programmable Gate Array for the assessment of power consumption and computational complexity for the different mathematical operations used in the DSP system algorithms. This paper focuses on the development of a novel metric to map the power consumed to the complexity of computing using the mathematical operations of the wireless system transceivers. This makes it possible to combine complex computation metrics for every single operation of mathematical computing. Thus, the whole algorithm can be described by a single metric, making comparison with other algorithms easier, besides being informative. This approach is useful in assessing the computing power of various algorithms involved in DSP wireless communication systems, which, in turn, makes it possible to compare the complexity involved in computing the various systems, which in most cases is misleading. Based on the assessment of the power consumption of a few DSP algorithms, it is evident that higher power is required by some algorithms because they are not suitable for systems operating at constrained power in wireless communication. The proposed method can also be used to implement different hardware systems with the required calibration to be adapted to the platform.