An ultra-narrow FinFET poly-Si gate structure fabricated with 193nm photolithography and in-situ PR/BARC and TEOS hard mask etching

A vertical double gate MOSFET (FinFET) device with an ultra-small poly-Si gate of 30nm and promising device performances has been successfully developed after integrating a 14a nitrided gate oxide on silicon-on-insulator (SOI) wafers. First, a 500a-thick TEOS capping oxide layer was deposited upon a 1000a-thick poly-Si gate layer. Second, both 1050a-thick bottom anti-reflective coating (BARC) and 2650a-thick photoresist (PR) were coated. A deep ultra-violet (DUV) 193nm wavelength ASML scanner lithography tool was used for the ultra-small poly-Si layout patterning under high energy exposure. After an organic-based trimming down plasma etching of both PR and BARC, the TEOS capping oxide layer was plasma etched in another oxide-based etching chambers without breaking the plasma etcher's loadlock vacuum. Then, without removing the already plasma patterned and trim-downed PR and BARC, an in-situ PR/BARC and TEOS hard mask etching was rendered for the final 1000a-thick poly-Si gate electrode. The poly-Si etching can be automatically stopped by setting the over-time etching mode to a few seconds after detecting the endpoint signal of the bottom buried oxide (BOX) insulating layer. Finally, after PR and BARC plasma as well as additional wet cleaning, an ultra-narrow poly-Si gate electrode, i.e., after etching inspection (AEI) of 30nm, with its capping TEOS hard mask was successfully fabricated.