Session 8 overview: Low-power digital circuits
2016
Energy efficiency continues to be a key driving force in digital circuits. The 8 papers in this session describe innovative low-power digital design techniques. Contributions include a 3D circuit using an asynchronous network-on-chip, two new design approaches for LDOs, and a technique for monitoring delay degradation to trigger adaptive voltage scaling. In addition, papers describe a fully integrated PMU with switched capacitor DC-DC converter, a balanced charged-recycling bus in a 16nm FinFET process, a Physically Unclonable Function (PUF) for security applications, and an iRazor error detection and correction design approach.
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