Effects of Hafnium Oxide on Short Channel Effects and DC Analysis for Double Gate Junctionless Transistors

In this paper, a silicon based two dimensional (2D) double gate junctionless transistor (JLT) is analyzed for its functional understanding and performance optimization feasibility. The DC characteristics and short channel effects (SCEs) analysis are performed for the proposed JLT structure. JLT with different structural parameter variation like gate length (10–80 nm), oxide thickness (1–5 nm), doping concentration (1 × 1015–1 × 1019 cm−3), and raising source and drain thickness are investigated. The effect of these parameters and dielectric variation on the threshold voltage, drain current, transconductance, drain induced barrier lowering (DIBL) and subthreshold swing (SS) of the junctionless transistor also evaluated and analyzed. The analysis shows that the threshold voltage of JLT can be tuned by controlling device structural parameters. Further variation in gate oxide shows that JLT with hafnium oxide (HfO2) gives better device characteristics compare to JLTs with silicon nitride (Si3N4) and silicon-dioxide (SiO2). Use of high-k dielectric in gate oxide improves the JLT with respect to DIBL and SS. By choosing the proper channel doping, gate dielectric and their thickness combinations, the desired device characteristics could be obtained for junctionless transistor.