Efficient Test Generation Framework for Analog LSI with Behavior Model : (Invited Paper)

Due to shrunk manufacturing process of LSI, test costs of analog LSIs are increasing. DC test method is the structural test using the DC signal. Structural test can test DUT in short time. DC test can reduce test cost of Analog LSI. We have developed an automatic DC test generation framework. The generated test pattern can discriminate between process variation and true faults. In order to reduce the test pattern generation time, we propose two methods. One is to reduce the number of simulations using circuit layout information. The other is to reduce the circuit simulation time using the analog behavior model. The effectiveness of the proposed method is shown by test generation experiment. Experimental results suggest that the proposed method is effective for large and complicated analog circuits.