Power delivery design and analysis on a network processor board

The power delivery design and analysis method is presented on a network processor board design. The design is accomplished by placing a large number of capacitors in the pin field using a via sharing pattern, and adding embedded capacitance with extra power planes to optimize the power delivery network. The innovative design reduced the voltage droop and resistive loss. Measurements were made and the design was validated. A full-scale analysis of power delivery network was performed with rigorous model extraction. The simulation results correlated well with the measurements.