HLS-Based FPGA Acceleration of Building-Cube Stencil Computation

This paper presents design and implementation of a framework for high-level synthesis (HLS), which allows easy description and acceleration of stencil computation with building-cube method (BCM) on FPGAs. The BCM is one of adaptive mesh refinement methods, which can reduce computational costs by using various granularity of cubes depending on computational precision required by target models. By placing some restrictions on size ratios between adjacent cubes, the BCM offers affinity to parallel processing. However, non-continuous memory access imposed by the irregular cubes does not straightforwardly match with stream processing on FPGA accelerators. To fill this gap, we design and implement a BCM framework as a class library on a high-level synthesis environment. The framework automatically generates mechanisms required for the BCM, such as reordering modules of data streams and data interpolation hardware between different cubes. The proposed framework is evaluated in terms of computing performance, memory performance and required hardware resources on a Maxeler Technologies FPGA accelerator. The results reveal that a performance overhead of data exchange between different sizes of cubes is reasonably small.