On the General Mathematical Framework, Calibration/Compensation Method, and Applications of Non-Ideal Software Defined Harmonics

Recently harmonic interference rejection has been recognized as a crucial bottleneck of truly wide-band software defined radio transceivers. Phase and gain mismatches among mixing paths, typical for nanoscale technology nodes, severely im- pact the achievable rejection ratio in classical harmonic rejection transceivers. This paper proposes an alternative digital intensive architecture, which enables increased harmonic interference rejection for wide-band SDR transceivers impacted by severe gain and phase mismatches. A generic mathematical framework of the target architecture is introduced to support a systematic design space exploration for multi-path harmonic interference rejection transceivers. With the framework, an iterative on-die estimation and compensation of mismatch for both the transmitter and receiver are presented. Case study with four mixing paths shows that ideal rejection can be achieved when targeting a single dominating harmonic interferer, and joint suppression of the 3rd and 5th order harmonic interferers of at least 70 dB can be obtained under realistic radio input scenarios.