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Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs
Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs
2013
Chizu Matsumoto
Yuichi Hamamura
Michinobu Nakao
Kaname Yamasaki
Yoshikazu Saito
Shun'ichi Kaneko
Keywords:
System on a chip
Redundancy (engineering)
Engineering
Fuse (electrical)
Electronic engineering
Embedded system
Wafer
random access memory
repair time
Correction
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