Performance Potential of Ge CMOS Technology From a Material-Device-Circuit Perspective

Recently demonstrated CMOS circuits based on Ge nanowires (Ge-FET) promise sustained technology scaling because higher mobility Ge guarantees target ${I}_{\text {ON}}$ at a lower ${V}_{{\textit {DD}}}$ . Unfortunately, this promise is counterbalanced by the fact that Ge is a poor thermal conductor, thus, the thermal confinement of the surround-gate topology may exacerbate self-heating (SHE) and erode the intrinsic performance gain associated with the high channel mobility. In this paper, we use: 1) electrical and optical methods to, respectively, characterize channel and surface SHE of Ge-FET with various channel lengths ( ${L}_{\text {ch}}$ ), widths ( ${W}_{\text {ch}}$ ), and the number of the nanowires (NWs) (#NW); 2) interpret the results obtained by the 3-D thermal modeling, and compare theoretically the SHE in Ge-FET configured in various topologies, such as bulk FinFET, silicon-on-insulator FinFET, and gate-all-around NW-FET; and 3) embed the results in an electrothermal SPICE simulator to compare the performance of ring oscillators based on Ge-FET and Si-FET. Our results show that the existing Ge-FET (with an airgap) is thermally suboptimal, but once optimized, SHE in Ge-FET would be comparable to that of Si-FET. The results encourage sustained development of Ge-FETs.