A Low-Cost Strained Silicon SRAM Technology with Reduced Contact Resistance

This paper presents a simple and cost-effective method to enhance 65nm SRAM technology performance using a single stress liner, resulting in 25% increase in cell read current. A novel slot contact process allows significant improvement of NMOS drive current without PMOS degradation, by relaxing the undesirable strain in the PMOS. This new slot process also results in significant reduction of the S/D contact resistance.