FinFET device with Silicon-Germanium alloy layer

A fin field effect transistor (FinFET) structure and method of making the FinFET including a silicon fin that includes a channel region 154 and source/drain (S/D) regions 156, formed on each end of the channel region 154, where an entire bottom surface of the channel region 154 contacts a top surface of a lower insulator 722 and bottom surfaces of the S/D regions 156 contact first portions of top surfaces of a lower silicon germanium (SiGe) layer 120; the FinFET structure also includes extrinsic S/D regions 456 that contact a top surface and both side surfaces of each of the S/D regions 156 and second portions of top surfaces of the lower SiGe layer 120; the FinFET structure further includes a replacement gate or gate stack 884 that contacts a conformal dielectric 882, formed over a top surface and both side surfaces of the channel region 154, that is disposed above the lower insulator 722 and not above the first and second portions of the lower SiGe layer 120, in which the gate stack 884 is electrically insulated from the extrinsic S/D regions by the conformal dielectric. Also disclosed is a similar FinFET were the SiGe layer 120 is replaced with an insulating material.