An Improved HEXBS Motion Estimation Algorithm and Hardware Design for H.264/AVC

Motion estimation plays an important role in the H.264 video compression, it occupies most parts of the entire computation. An improved hexagon-based search algorithm (HEXBS) and its hardware implementation is proposed. The number of the search points of the first template is reduced. The improved algorithm adopts two types search pattern: large cross search pattern and small cross search pattern. In addition, the algorithm can make full use of hardware resources, it works in a parallel way efficiently and is able to process very high definition real-time videos. The proposed architecture is simulated by Modalism 6.5 SE, synthesized to the Xilinx Virtex4 XC4VLX15 FPGA device. The simulation results show that this architecture can achieve 110MHz, and 140M pixels can be processed per second, which meets the requirements of real-time applications.