Tools for On-Chip Interconnect Inductance Extraction

For years the focus of analyzing interconnect has been in getting accurate capacitance and resistance parasitics. But what about this parasitic called inductance? Where did it come from and why is there so much interest in it today. Inductance has always been a parasitic in interconnects but it is just starting to become significant in today’s DSM high speed SOCs and RFIC designs. OEA International delivers tools which help you understand if unintentional inductance effects are important in your digital or RF/analog designs and help predict accurate inductances in designs where inductance is designed into circuit components.