Study on design rule verification procedure of semiconductor memory devices by using design based metrology (DBM)

At the early stage of development of semiconductor memory devices, design rule should be defined for providing design guidelines to the design engineers. Those design rules are usually expressed in terms of minimum sizes of simple patterns which describe lithography and process limitations. However the real chip designs consist of a variety of complex patterns, so minimum size design rules of simple patterns are not enough for optimizing design layout. Therefore, design rules considering various design patterns are more advisable rather than simple minimum rules. But it is not easy to setup those design rules due to the difficulties of a large number of pattern verification. In our work, we evaluate design rule verification procedure by using Design Based Metrology (DBM) to overcome the difficulties of inspecting many type of patterns. We designed a large number of test patterns including various 1D and 2D design structure. And those patterns could be inspected at a fast speed with a design based metrology. From all the measurement data, the proper design rules successfully introduced and verified. Finally we found out the suggested procedure is a suitable method for verifying design rules.