Interfacing Architecture between Telemetry and On-Board Computer for a Nanosatellite

Team Anant, a student team is developing a 3U Nanosatellite with a hyperspectral camera as the payload. The proposed satellite is divided into multiple subsystems. Linking and coordination amongst them have been done based on satellite constraints. The satellite follows a combination of centralized and distributed architecture. This paper details the architecture of the interface between the On-Board Computer(OBC) subsystem and the Telemetry Tracking and Command (TTC) subsystem. The Telemetry microcontroller handles data downlink and error control. OBC handles payload camera operations and image compression. To make the system full duplex, one of the cores on OBC is dedicated to the uplink circuitry. Hence, re-transmission requests and acknowledgements from the ground station are received by OBC. This necessitates a proper interface between On-Board SoC and telemetry microcontroller which is done using the UART protocol. The On-Board Computer of the satellite acts as the primary source of all the commands and monitors the status of the various subsystems. Its architecture performs hyperspectral image compression on a Field Programmable Gate Array (FPGA) before the image gets downlinked to the ground station. The algorithm used for the same is CCSDS 1.2.3. Storage and downlinking of payload and housekeeping data are aided by a subsystem specific interface architecture. The image is transferred from Payload to an on-board memory from where it is fetched by the FPGA in tiles for compression. The compressed data is pushed in the FIFO and stacked in its buffer. Subsequently, the telemetry microcontroller pops out the data whenever it is required to be packaged before downlinking. Therefore, FIFO hardware guarantees a sequential flow of data from OBC to telemetry without explicitly knowing the memory addresses of the compressed image. Moreover this FIFO memory is also used for sending housekeeping data. Thus, this paper will be elucidating the concepts of interfacing between the different subsystem's microcontrollers with the management of shared memory.