A High-Speed FPGA-based Implementation of Inverse Integer Transform Algorithm of H.264

H. 264 uses integer transformation approach in order to exploit the spatial redundancies in video sequences. This paper proposes efficient hardware design for implementing inverse integer transform of H.264. The hardware uses minimum adders and shifters and the datapath of the design is reconfigurable while being able to process HD frames in real-time. This designed is targeted to be integrated as a constituent of an entire H.264 based system. Using Xilinx Virtex-4 device, the presented architecture has been verified to operate at a maximum frequency of 165 MHz.