Issues and Challenges of Cleaning for Nano-Scale NAND Flash Memory Manufacturing

Recently, NAND flash memory has been used widely for various mobile electronic appliances. Due to strong demand for the non-volatile memory of low cost and high density, the design rule of NAND flash memory has been moving toward sub-50 nm regime. As the flash memory device shrinks to nano-scale, the control of defects and particles on wafers is the most critical task for achieving high yield. The preparation of ultra clean and flat wafer surface is a great challenge of wafer cleaning and an absolute prerequisite for the defect-free process. In this paper, current issues and challenges of cleaning and surface preparation in nano-scale flash memory manufacturing are discussed. . The characteristics of the cleaning process for the flash memory are related to device structures and integration schemes. In comparison to other IC devices, the unique device structure of a flash memory is a floating gate as a memory cell unit. One of critical steps of the flash memory process integration is the control of effective field oxide height by wet etchback. The field oxide height affects the coupling ratio and the threshold voltage of a cell transistor. A challenge in the wet etchback is to achieve the formation of uniform and robust field oxide within both chip and wafer.