Overview of Carbon Nanotubes for Horizontal On-Chip Interconnects

The extraordinary development of micro- and nano-electronics is based on the brilliant idea of Gordon Moore, Robert Noyce, and others who proposed in the early 1970s a model development based on the shrinking of the integrated structures (transistors, connections) in the chips. This provides a long-term road map for technological development as well as a very efficient economic model. The size reduction, all other aspects being equal, results in performance improvements related to the possibility of making faster and more complex devices on the same area of silicon. Each node, typical scale length of the components, follows the same development cycle with massive investments for production and a return on investment at the end of the cycle related to the fact that better-performing, cheaper devices flood the market. The idea was also that the performance improvement was mostly a continuous process and not based on technological breakthrough at each node. Indeed it is reasonable to anticipate that such breakthroughs take a considerable amount of time to be fully realized and implemented. Initially the performances of the chips were largely limited by the active components which are the transistors. Since the mid-1990s this situation is completely reversed and now the chips are limited by interconnects. These limitations are so serious that they contribute to slowing down the microelectronic road map. A first revolution in the field of interconnects was the replacement of aluminum wires by copper wires and the introduction of low K dielectric materials instead of more conventional ones. To overcome current limitations a new material revolution is probably mandatory. Carbon materials such as carbon nanotubes, thanks to their superlative physical properties, can be the future material of choice.