Integrated intelligent page detector

The system comprises: a CPLD logic control circuit, a DSP processing circuit, a CMOS sensor circuit, a memory expanded circuit, a USB communication and serial-port communication circuit, and an interface circuit. The CPLD is taken as the core logic control unit; the DSP is taken as the image collector and signal processor. The apparatus uses 300,000 pixels CMOS image sensor to get highly-detailed,high-definition and high-precision images.