Convolution Processing Unit Featuring Adaptive Precision using Dynamic Reconfiguration

As the demand of low latency machine learning IoT devices has rapidly expanded in the past decade for commercial and industrial applications, cloud computing models have relied on high-speed connectivity which many devices do not have access to. Cloud based solutions are also becoming less attractive for inference solutions with arising privacy and security concerns. Transitioning computation towards edge devices is becoming essential and finding ways to make such computer vision workloads operational on constrained IPs is a key element in this work. As edge devices are limited in processing resources, relying on reconfigurable hardware such as FPGAs will offer an embedded platform to dynamically shape the IPs and cores as needed for each specific application working on it. Convolutional Neural Networks and alike computer vision techniques rely heavily on computation and matrix based operations, this paper proposes a dedicated convolution processing element. The proposed a convolution processing element is implemented on a Pynq-Z2 FPGA that supports Dynamic Partial Reconfiguration between integer point convolution operations of 8, 16, and 32 bit precision. The use of Dynamic Partial Reconfiguration at a processing element level enables the design to be reconfigured 800× more quickly than traditional methods while minimally increasing system overhead.