A Design of Low Power and High Speed Encoder and Decoder Circuits by Re-Evaluating High Speed Design Values

Nowadays, the rapid improvement in CMOS technology to reduce power and area and to increase the speed of chip is mainly consideredin research field. In this paper power dissipation and delay are reduced using Transmission Gate Logic(TGL), which are the most challenging factor in CMOS VLSI Design. The power reduction is achieved without compromising the performance. It is difficult to design such devices because tradeoff between power consumption and speed is a major concern. The encoders and decoders in this paper are designed using proposed TGL by which trade off problems can be eliminated to a greater extend. The number of transistors reducedis four in AND Gate. In OR Gate the power is reduced more than half even with two transistors increased in proposed design. The circuits are designed using 45nm technology in CADENCE VIRTUOSO and the performance parameters are analyzed.