Resolution of disputes concerning the physical mechanism and DC/AC stress/recovery modeling of Negative Bias Temperature Instability (NBTI) in p-MOSFETs

Negative Bias Temperature Instability (NBTI) is due to interface trap generation (ΔN it ) and trapping of holes in gate insulator traps (ΔN It ). However, the isolation methods and the relative dominance of ΔN it and ΔN it , time constants of ΔN it and ΔN it for stress, recovery and associated temperature (T) activation, and whether ΔN it recovers or remains permanent after stress, are widely debated. The resolution of such disputes is necessary to develop a reliable NBTI model. This work uses carefully designed measurements and simulations to resolve the aforementioned disputes. The contribution of ΔN it and ΔN it on overall threshold voltage shift (ΔN t ) is determined. Kinetics of ΔN it and ΔN it during stress and recovery, T activation and associated time constants are verified in both large and small area devices. Existing theoretical models for ΔN it and ΔN it are benchmarked and validated against DC and AC experiments. Capability of the existing models for predicting end-of-life ΔN t is demonstrated.