New process variation modeling method of 3-D capacitances for advanced nanometer CMOS

Modeling the 3-D capacitances of FinFET devices, shown in Figure 1 [1], accurately is critical for the continuing scaling of CMOS nodes. Without accurate capacitance and process variation modeling, the yield of advanced nanometer CMOS nodes will decease due to high timing mismatch. In this paper, we propose a new process variation based characterization to enable R&D engineers to identify critical process parameters for realistic process optimization, thus leading to reduced power consumption, higher electrical performance, smaller area, lower cost, and shorter time-to-market.