A new dynamic gate capacitance measurement protocol to evaluate integrated high-voltage devices' switching loss performances in power management applications

A novel dynamic gate capacitance characterization technique is proposed to evaluate switching losses in power devices. Dynamic gate capacitance is obtained by measuring the gate displacement current due to the application of a controlled gate voltage pulse, closely matching real operation conditions of power switches. Several architectures for 20-V MOSFET transistors, integrated in a low-cost power management 0.13-/spl mu/m CMOS technology, are studied. Experimental results are compared to a specific small-signal model for switching transition gate capacitance.