Mismatch compensation of a subthreshold CMOS current normalizer

This paper presents a current normalization circuit with floating gate mismatch compensation. Normalization circuits are an important class of signal processing architectures, and although subthreshould MOS devices can efficiently implement these systems, their precision is often limited by fabrication mismatch. A current normalizer with outputs inversely proportional to the input signals was designed and simulated for a commercially available 0.5µm CMOS process. We show that through self-limiting floating gate mismatch compensation techniques the process induced system mismatch can be reduced by 78%.