Performance/reliability trade-off in superscalar processors for aggressive NBTI restoration of functional units

Negative-Bias Temperature Instability has become a serious reliability concern in modern processors design, and in the last decade many research effort has been spent in developing circuit-level and architecture-level strategies to mitigate the induced delay variation of nanoscale circuits. At the architecture level, work has been proposed to alleviate this by appropriate dynamic instruction schedulingntechniques. However, their benefit is bounded to the available redundancy, limiting their attractiveness for a cost-effective VLSI solution. This paper presents an in-depth analysis of a performance reliability trade-off FSM design, that is able to attain the desired level of reliability improvement according to the ILP performance constraints. Power-gating is used for aggressive NBTI restoration. Extensive experimental results show several performance reliability trade-off examples in a broad range of application scenarios.