Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses

The paper proposes a bus architecture which improves the performance and/or power dissipation of online buses. The proposed architecture reduces the delay on alternate lines by lowering its repeaters' threshold voltages, V/sub t/. Furthermore, the shifting of the signal switching on adjacent lines reduces the worst-case coupling capacitance. Two implementations of this bus architecture are proposed, the alternate-V/sub t/ (AVT) and the alternate forward body bias (ABB) schemes, and are compared to a conventional bus (CB) scheme. For a flop distance of 1800 /spl mu/m, the proposed schemes use the gained delay slack to reduce the total device width, thus reducing the energy dissipation by 31.2%. For a 500 ps cycle time, the proposed bus schemes increase the maximum distance between flip-flops by 33%.