language-icon Old Web
English
Sign In
Acemap > Paper > A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS

A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS

2014 
Keywords:
    • Correction
    • Source
    • Cite
    • Save
    • Machine Reading By IdeaReader
    8
    References
    4
    Citations
    NaN
    KQI
    []
    logo
    • CCF Conference Analysis
    • Map Galaxy
    • What's New
    © Copyright 2015-2020 Acemap, Inc. Shanghai Jiao Tong University.