Compact storage arrays

Memory cell array, comprising • first gate lines, the second gate lines, and third gate lines which are disposed over a substrate, wherein the second gate lines between the first gate lines and the third gate lines are arranged, and wherein the first gate lines, the second gate lines and the third gate lines form adjacent gate lines of the memory cell array; • first metal lines, which are arranged over the first gate lines and extending in the direction of the first gate lines, wherein the first metal lines are electrically coupled to the first gate lines; • second metal lines, which are arranged over the second gate lines and extending in the direction of the second gate lines, wherein the second metal lines are electrically coupled to the second gate lines; • third metal lines, which are arranged over the third gate lines and extending in the direction of the third gate lines, wherein the third metal lines are electrically coupled to the third gate lines, wherein the first metal lines, the second metal lines and the third metal lines are disposed in different metallization; • with first portions having contacts that electrically couple the first gate lines only with the first metal lines; • with second regions that couple the second gate lines with the second metal lines electrically; • each of said first metal lines has a first portion which comprises at least one of the first regions, and a second portion at least adjacent one of the second regions, each of the second portions of the first metal leads in the direction of the first gate lines with respect to a the first portion of the corresponding first metal lines is offset.