Low‐voltage rail‐to‐rail switched buffer topologies

This paper presents some CMOS rail-to-rail low-voltage (1.2 V) switched buffer topologies, to be used as input stages in switched-opamp circuits. The main buffer is based on the use of an op-amp featuring rail-to-rail input and output swing with constant transconductance over the input common mode voltage. The designed buffer exhibits a total harmonic distortion of about -61 dB for 5 MHz clock frequency with 2 Vpp input amplitude. Its characteristics have been compared with those of other rail-to-rail switched buffers, based on the main CMOS OTA (simple, symmetrical, Miller), showing good distortion even at frequencies in the MHz range and satisfying the requirements for the series switches. Copyright © 2001 John Wiley & Sons, Ltd.