Circuitry for generating the sampling clock in a device for serial examination of the operation of an integrated circuit

The circuit comprises first switching means (11) which receive at input a system clock (XTALIN) normally provided for the operation of the integrated circuit and produce at output a machine clock (CK) normally coincident with the system clock (XTALIN), means for clamping (13) the first switching means (11) which after a firing signal of the serial analysis (ENSH) determine the clamping of the state of the machine clock (CK) and second switching means (14) which receive at input the system clock (XTALIN) and are fired by the firing signal (ENSH) to produce a scanning clock (SCK) which repeats the system clock (XTALIN) in an inverted or non-inverted manner according to the state in which the machine clock (CK) has been clamped.