Session 30 Overview: Non-Volatile Memories Memory Subcommittee

A 3D NAND flash memory continues to increase in bit density and performance for both local and cloud data storage applications. The number of WL layers increases to more than 170 layers, up from 96-128 layers presented previously at ISSCC. A floorplanning technique used to put page buffer circuits into a small area under a highly-stacked memory array is shown in paper 30.1. Paper 30.2 and 30.4 present independent multi-plane read techniques to improve random read performance. Paper 30.3 and 30.4 reveal high-speed 2.0Gbps interfaces.