The processor and compiler

The present invention provides a small circuit scale, low power consumption and can be performed at high speed processor processing cycle, the arithmetic unit includes a decoding unit and the like, when the decoded instruction decoding unit [jloop C6, C1: C4, TAR, Ra], the to execute a series of processes, i.e., (1) in the case of register Ra is less than 0, the condition flag C4 is set to 0, (2) transfer the values ​​to the condition flag condition flags C2 C1, C3 conditional flag value is transferred to the condition flags C2, C4 conditional flag value is transferred to the condition flag C3 and C6, (3) adding -1 of register Ra, and stores in the register Ra, (4) branches to the branch register (TAR) as shown in the address . In the case of a jump instruction in the branch target buffer unfilled, filled with the branch destination instruction.