Semiconductor memory device and system for a semiconductor memory device

Semiconductor memory device comprising: a plurality of ports (POA, POB); at least one shared memory area (102) of a memory cell array (100) can be accessed through the ports (POA, POB); and a data transfer control unit (120) which is coupled to the shared memory area (102) and the ports (POA, POB), said data transfer control unit (120) is adapted to a read command (BR) of a plurality (of read operation commands BR, B- PRE), which (via a first port of the plurality of ports during a read operation to the shared memory area 102) are received, according to a write command (AW) of a plurality of write commands (AA, AW) which, via a second port of said plurality are received by ports in the context of a write operation to the shared memory area (102) to be applied before any other commands that are associated with the read operation and the write operation to the shared memory area (102) are applied when at least a portion of a write address, is associated with the write operation, and at least a part of a read address of the read operation Settings associated is Et, are substantially equivalent, wherein the data transmission control unit (120) comprises: an instruction decoder (122) coupled to the ports and arranged to combine through the ports received signals associated with the read operation and the write operation, and which is adapted to generate a port decode signal; and ...