Low power AES encryption using asynchronous NCL method

Power consumption of the electronic devices become one of the major concerns in synchronous circuits, asynchronous designs, especially null convention logic (NCL), is gaining more increasingly attention. The NCL methodology eliminates the prolems related to noise, clock tree, electromagnetic interference and also reduce significant power consumption. In this paper, we propose the two AES encryption models using the synchronous circuit design technique and the asynchronous circuit design technique based on NCL. The AES Encryption model based on NCL is a delay-insensitive logic paradigm. Besides, both synchronous and asynchronous AES encryption circuit models are realized using VCS tool to simulate and DC tool to synthesize parameters in power consumption, processing speed and area. The synthesis results of the two models indicated that power consumption of the the NCL based asynchronous  AES encryption model has a decrease of 71% compared with the synchronous AES encryption model while the area of the synchronous AES model is smaller than that of counterpart. This work could help the IC designers to choose the appropriate design model.