A triple-mode LDPC decoder design for IEEE 802.11n SYSTEM

This paper shows a triple-mode LDPC decoder design with two design techniques, the matrix reordering algorithm for multi-mode reconfiguration and the Single-Entry-Multiple-Data (SEMD) scheme for throughput enhancement. The matrix reordering algorithm can reduce the computational complexity from O(n!) to O(n 3 ). The SEMD can enhance the throughput by m times with small area overhead. With TSMC 0.13µm CMOS, the proposed design is synthesized in 1.99mm 2 area at 172.4MHz.