A 2.0-2.9 GHz Digital Ring-Based Injection-Locked Clock Multiplier Using a Self-Alignment Frequency Tracking Loop for Reference Spur Reduction
2020
This paper presents a 2.0-2.9 GHz digital ring-based injection-locked clock multiplier (ILCM) in a 65 nm CMOS process. A self-alignment frequency tracking loop (SA-FTL) with background delay calibration is proposed to improve the accuracy of injection timing. Since the frequency mismatch of the free-running oscillator and the target frequency is minimized without delay error, the reference spur is reduced to -55.6 dBc, exhibiting 15.9 dB improvement comparing to the case that the SA-FTL is off. The proposed ILCM achieves 545 fs RMS jitter at 2.5 GHz output frequency with a power consumption of 3.1 mW, achieving the FoM of 240.3 dB.
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