Enhanced state monitor for scan test

The present invention relates to an enhanced state monitor for scan test. An integrated circuit is disclosed. The integrated circuit receives test control information which is written onto a scan clock for testing a scan chain in an IC through phase encoding, wherein the phase encoding does not affect the normal use of the scan clock and the scan test chain and allows additional relevant data (such as power source, clock and additional global and specialized state data) to be collected by an auxiliary test data storage system (such as a shift register), and the phase encoding further controls selective output of enhanced test states or traditional scan test output.