FPGA Implementation of Adaptive Non-linear Predictors for Video Compression

The paper describes the implementation of a systolic array for a non-linear predictor for image compression. We can implement very large interconnection layers by using large Xilinx and Altera devices with embedded memories and multipliers alongside the projection used in the systolic architecture. These physical and architectural features create a reusable, flexible, and fast method of designing a complete ANN (Artificial Neural Networks) on FPGAs. Our predictor, a MLP (Multilayer Perceptron) with the topology 12-10-1 and with training on the fly, works, both in recall and learning modes, with a throughput of 50 MHz, reaching the necessary speed for real-time training in video applications.