A digitally stabilized type-III PLL using ring VCO with 1.01ps rms integrated jitter in 65nm CMOS

The design of low-jitter VCO-based PLLs is quite challenging as high VCO control gain, K VCO , increases the phase noise contribution arising from the charge pump and loop filter. To resolve this problem, dual-tuning PLLs (DT-PLLs) have been studied [1–4]. The DT-PLL structure adds a narrow-bandwidth coarse (high-K VCO ) path to the fine (low-K VCO ) path consisting of a type-II PLL. The narrow-bandwidth analog filter in the coarse path plays an important role in preventing the charge pump and the loop filter from increasing the output jitter, while a wide-tuning range is maintained. Moreover, the coarse path adds another pole at origin to the fine path and transforms it from a type-II to type-III PLL [3–4]. Compared to a type-II PLL, owing to its boosted low-frequency loop gain, a type-III PLL can better suppress a low-frequency disturbance to the ring VCO, such as temperature drift. However, a type-III PLL has stability problems. To ensure sufficient phase margin (PM), a type-III PLL requires an extremely narrow-bandwidth (e.g. ∼10–100Hz) analog filter in the coarse path or must make the K VCO of the fine path larger. The former requires a nano-Farad capacitor or a fairly complex design for shrinking the capacitance, while the latter way increases total jitter.