Programmable step delay time base and sampling system

The utility model relates to the technical field of electrical equipment, in particular to a programmable step delay time base and sampling system, which comprises a clock module, a CPU/FPGA control module, a coarse delay module and refined delay module. The clock module generates three channels of synchronous sampling triggering signals for the sampling system via preset triggering frequency at preset triggering time, the first channel of synchronous sampling triggering signals is transmitted to the CPU/FPGA control module to form AD sampling control signals, the second channel of synchronous sampling triggering signals is sent to a pulse source to form pulse source triggering signals, and the third channel of synchronous sampling triggers is sent to the coarse delay module and the refined delay module and then sent to a sampling head after being delayed in preset time to form accurate programmable step delay gating sampling head triggering signals which can be accurately synchronous to repeated triggering pulse signals to generate wide-range and accurate step delay sampling signals. The programmable step delay time base and sampling system can accurately sample signals with long period and low duty ratio at fixed time, and has the advantages of simple implementing, convenient debugging, capacity of avoiding noise and temperature influence and the like.