Performance optimization issues in sequential logic synthesis

In this thesis we have looked at various ways to improve the performance of a sequential circuit. In particular, an important problem of multi-cycle false path removal from sequential circuits was studied in detail. The thesis presents certain observations and discusses properties of multi-cycle false paths at various levels of abstraction. A thorough and complete analysis of multi-cycle false paths at the logical, functional and behavioral level is presented and the relationship between the various levels is explained. The thesis presents a method to identify and remove false paths at the functional level and a method for the prediction of false paths at the behavioral level. The thesis also describes an efficient method utilizing high level information for timing verification and test generation. The necessary and sufficient conditions to remove multi-cycle false paths is derived and a constrained satisfaction based direct encoding methodology to obtain false path free sequential circuits is presented. A simple formula for the minimum number of registers needed for such an encoding is also derived.