A soft error immune 0.35 /spl mu/m PD-SOI SRAM technology compatible with bulk CMOS

It has been noted that the soft error rate of the partially depleted SOI (PD-SOI) SRAM is not improved as compared with bulk CMOS SRAMs due to floating body effects through simulation (Tosaka et al. 1995). There has been no soft error data reported in the papers on SOI SRAMs, except for those used for space applications. In high-density PD-SOI SRAMs, a body contact is essential to reduce soft error rates. It has been proposed that a thin well layer left between the isolation and the buried oxide can provide a convenient body contact layer that has no area penalty and is compatible with bulk CMOS (Chen et al. 1996). However, soft error data and the required body contact resistance needed to suppress the floating body effect has not been clear. Thus, we have fabricated 288-kbit SRAM test chips with 0.35 /spl mu/m CMOS technology and confirmed that the soft error rate can be improved. We also estimated the body contact resistance required for soft error improvement through device simulation.