Asynchronous Architectures for Large-Integer Processors With Applications to Security

Abstract : The objective of this research was to develop new architectures for cryptographic hardware that offer extremely high throughput, algorithm flexibility and system upgradability, radiation hardness by design, and low power. The feasibility of an asynchronous (clockless) architecture combining a dedicated large integer processor, an FPGA, and a simple processor was investigated. A novel approach to making asynchronous circuits SEU-tolerant was developed and simulated. Simulation and analysis demonstrate that such an architecture combines high throughput, adaptability, and excellent resistance to SEUs. The systems envisioned would be built out of quasi-independent components that can be commercialized stand-alone and in different configurations, enhancing the upgradability and flexibility of the product range.