Electrical Failure Analysis Methodology forDRAM of80nmeraandbeyond using Nanoprober Technique

Inthis paper, theelectrical failure analysis for performance ofperiphery andcellarray transistors. lOMm DRAM ofdesign rule as80nmandbeyond byusing nanoproberand1Mmactive widthsizetransistors weretested for technique wasdescribed. We havesuccessfully measured and periphery transistors alsowere 140nmgatepitch cell evaluated electrical characteristics ofperiphery andcell array tranistos o8Om DRA usngnnoprberMeauremnts transistors. lOxiOmfm sizesamples werepolished using the transistors of80nmDRAM using nanoprober. Measurements forMetalContact (MC), BitLine(BL)andBitLineContact dimplegrinding methodandtreated byBuffered Oxide (BLC)probing wereproceeded andcompared withTest Etchant (BOE)torecessoxidelayer infewseconds and ElementGroup(TEG)probingresults. Interconnect cleaned byDIwater. After drying waterbytheinfrared lamp, Characterization Environment (ICE)simulation was also asample wasloaded inthespecimen vacuumchamber ofthe carried outtoverify thecurrent decrease ofBLC probingnanoprober. Theprobeunitofnanoprober (Hitachi, model results. Measurement forcharacteristics ofmemorycell array N-6000)had6 maximumtungsten (W) probesand transistors, whichhad150m pitch, of80m DRAM was controlled bythepiezoelectric driving. Theradius ofprobe possible. Itisconcluded thatadirect probing methodusing the nanoprober technique was an useful tooloftheelectricalTip wasct5n andeteresistane ofpoeelfwas20n failure analysis for80nmDRAM andbeyond generations. Theelectron accelerating voltage oftheelectron beamgun was 2kVandtheimage shift rangewas about± 100,mat roomtemperature.