Reliability of thyristor-based memory cells

This is the first published study of the reliability of Thyristor-based high-speed memories. The T-RAM (Thyristor-based Random Access Memory) was characterized using test structures and multi-megabit product die fabricated in a 130nm SOI logic technology. The reliability lifetime of a nominal bit was investigated by subjecting TCCT devices (Thin Capacitively Coupled Thyristor) to a DC current stress. The resulting acceleration model yields a lifetime of 1.0E+40 yrs for the Data-1 state and 1.0E+5 yrs for the Data-0 state. These long lifetimes are consistent with the 26 FIT long-term failure rate found for 9 Mb arrays, from dynamic lifetest on 9Mb & 18Mb T-RAM product die having full SRAM functionality. The susceptibility of T-RAM arrays to soft errors was assessed by accelerated neutron testing, and accelerated alpha testing, of 9Mb T-RAM product die as well as 9Mb SRAM product die from three suppliers. n-SER for the T-RAM is 610 FIT/Mb, better than the average of 700 FIT/Mb for 6T SRAM technology. Exposure of the T-RAM product die to X-rays showed that they tolerate doses of 450 rad or more (3–4x the dose for X-ray inspections) without degradation of nominal TCCT retention times, and without functional failure of memory cells. Taken together, the results of this study shows that T-RAM is a reliable memory technology.