A 6 mW 750 MHz anti-aliasing filter for receiver analog front-end

A low power high speed continuous-time filter for receiver application in standard 90 nm CMOS process is presented. A biquad cell based on the open-loop topology is implemented. Besides, a differential voltage buffer with additional gain boost, high linear voltage-to-voltage conversion and low output impedance is introduced. In this work, a fourth-order filter is implemented. Simulation results show the 750 MHz cutoff frequency with less than ?50 dB IM3 for a 300 mVpp input. The power consumption for this filter is 6 mW at a 1.2-V supply.