A logic chip delay-test method based on system timing

In this paper we present a novel approach to delay-testing of VLSI logic chips based on the level-sensitive scan design (LSSD) methodology. The objective of the delay test is to reduce significantly the failures of multi-chip modules at system integration test while minimizing the complexity and cost of subassembly testing. Because system timing data are used to derive test specifications, the delay defects that are most likely to cause a system path failure are detected a high percentage of the time. With the implementation of the delay test in the wafer production line, the system final-test failure rate of multi-chip modules used in IBM mainframe machines has dropped significantly.