On the rseries extraction techniques for sub-22nm CMOS finfet and SiGe technologies

Introduction: Series resistance (R series ) is a crucial factor for technology optimization and benchmarking [1–3]. R series is typically extracted in the bias conditions where R series dominates, i.e., linear regime and high Vgs by comparing multiple gate lengths. However this simple extraction is very challenging for sub22nm CMOS devices as changing a device length / width may change mobility or R series . For instance, this is the case for SiGe where the built-in stress effect [5,6] increases the channel mobility thus making the standard extraction difficult. The case is even more compelling for the bulk finfet case where the length width and height may not be known with the necessary precision and the gate stack itself may introduce (un)wanted stress components. As any R series extraction do rely critically on assumptions, in this paper we will first test the applicability and limits of several R series extraction techniques [1–3] and then use the best of both to gain new insights on the finfet and SiGe technology.